1. Field of the Invention
The present invention relates to a liquid crystal display device which can decrease the number of source drive integrated circuits ICs used to supply data, and also can decrease a flexible printed circuit and a printed circuit board to supply signals to the source drive integrated circuits ICs in size, and a method of driving the same.
2. Description of the Related Art
A liquid crystal display device displays picture images by controlling light transmittance of liquid crystal cells according to video signals. Particularly, an active matrix type liquid crystal display device is suitable for displaying moving pictures since it is provided with switching devices formed in the liquid crystal cells, respectively. In this case, the switching devices are generally formed of thin film transistors (hereinafter, referred to as “TFT”).
FIG. 1 is a schematic diagram of illustrating an active matrix type liquid crystal display device according to the related art. FIG. 2 is an equivalent circuit diagram illustrating a thin film transistor TFT array substrate with a 4×4 matrix type of ‘liquid crystal cells in a liquid crystal panel of the type shown in FIG. 1. FIG. 3 is a waveform diagram illustrating signals supplied to signal lines of a matrix type of liquid crystal cells shown in FIG. 2.
Referring to FIGS. 1 to 3, an active matrix type liquid crystal display device includes a liquid crystal panel 14 provided with a plurality of gate lines G1 to Gn, a plurality of data lines D1 to Dm, and a plurality of thin film transistors TFTs for driving liquid crystal cells Clc Each gate line is orthogonal to each data line, and each thin film transistor is formed adjacent to a crossing portion of the gate and data lines. A data driving circuit 12 is provided to drive the data lines D1 to Dm of the liquid crystal panel 14. A gate driving circuit 13 is provided to drive the gate lines G1 to Gn of the liquid crystal panel 14. A timing controller 11 is provided to control the data driving circuit 12 and the gate driving circuit 13.
The data driving circuit 12 is provided with a plurality of source drive integrated circuits ICs. Under the control of a timing controller 11, the data driving circuit 12 converts digital data to analog data voltages R1 to R4, G6 to G4 and B1 to B4 by using an analog gamma compensation voltage, and supplies the analog data voltages to the data lines D1 to Dm. Also, the gate driving circuit 13 includes a plurality of gate drive integrated circuits ICs. Under the control of the timing controller 11, the gate driving circuit 13 supplies scan pulses SP1 to SP4 to the gate lines G1 to Gn in sequence.
The respective scan pulses SP1 to SP4 are generated in about one horizontal period. Also, the data voltages R1 to R4, G1 to G4 and B1 to B4 are supplied to the data lines D1 to Dm in synchronization with the scan pulses SP1 to SP4. Then, the thin film transistors TFTs are turned-on in response to the scan pulses SP1 to SP4, whereby the data voltages output from the data lines D1 to Dm are supplied to pixel electrode PIX of the liquid crystal cells Clc. The liquid crystal cells Clc are arranged between the pixel electrode PIX supplied with the data voltage and a common electrode supplied with a common voltage Vcom. In this case, liquid crystal molecules are aligned based on an electric field generated by the pixel electrode PIX and the common electrode COM, to thereby modulate polarizing elements of incident light.
The timing controller 11 generates a gate control signal GDC to control the gate driving circuit 13 and a data control signal DDC to control the data driving circuit 12 by using horizontally and vertically synchronized signals H and V and clocks CLK. In this case, the data control signal DDC includes a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE, and a polarity control signal POL. Also, the gate control signal GDC includes a gate shift clock GSC, a gate output enable GOE, and a gate start pulse GSP.
In FIG. 1, ‘Cst’ connected to the liquid crystal cell Clc corresponds to a storage capacitor to maintain the voltage of liquid crystal cell Clc. The storage capacitor Cst may be formed in Storage-On-Gate method or Storage-On-Common method. In case of the Storage-On-Gate method, the storage capacitor Cst is connected between the preceding gate line and the pixel electrode PIX. In case of the Storage-On-Common method, the storage capacitor Cst is connected between the additional common electrode COM and the pixel electrode PIX. Also, the source drive integrated circuits ICs and gate drive integrated circuits ICs are bonded on a substrate by a Tape Automated Bonding (hereinafter, referred to as “TAB”) method shown in FIG. 4, or by a Chip On Glass (hereinafter, referred to as “COG”) method shown in FIG. 5.
In the TAB method of FIG. 4, the source drive integrated circuits ICs 51 and gate drive integrated circuits ICs 55 are respectively mounted on Tape Carrier Packages (hereinafter, referred to as “TCP”) 52 and 56. In this case, output pads of the TCPs 52 and 56 are adhered to data pads or gate pads of a glass substrate by anisotropic conductor film ACF. Also, input pads of the source TCPs 52 are adhered to output pads of the source PCB 53 on which the timing controller 11 and gamma reference voltage generation circuits (not shown) are mounted. Also, input pads of the gate TCPs 56 are adhered to output pads of the gate PCB 57. Then, the source PCB 53 is connected to the gate PCB 57 by an FPC 54. Through the FPC 54, driving voltages and control signals required for the gate drive integrated circuits ICs are supplied to the gate PCB 57 from the source PCB 53. In the COG method, the source drive integrated circuits ICs 61 and gate drive integrated circuits ICs 65 are directly adhered to a glass substrate by using conductive bumps, as shown in FIG. 5. In FIG. 5, ‘62’ corresponds to the FPC which is adhered to the glass substrate and supplies the voltage and signal required for the source drive integrated circuits ICs 61 and gate drive integrated circuits ICs 65 and generated from the source PCB 63.
In FIGS. 4 and 5, ‘50’ and ‘60’ correspond a pixel array where each of the data lines D1 to Dm is orthogonal to each of the gate lines G1 to Gn, and the liquid crystal cells Clc are arranged in the matrix configuration. In the liquid crystal display device, since the data lines D1 to Dm are arranged along the long-axis direction (X-axis) of liquid crystal panel 14, the number of data lines is larger than the number of gate lines. As a result, the number of the source drive integrated circuits ICs 51 and 61 for driving the data lines is increased. Also, since the unit cost of source drive integrated circuits ICs 51 and 61 is higher than the unit cost of gate drive integrated circuits ICs 55 and 65, it increases the cost of fabrication of the liquid crystal display device. Recently, in case of the liquid crystal panel 14 having XGA resolution (1024*768), if the source drive integrated circuits ICs 51 and 61 have 618 output channels, it necessarily requires five source drive integrated circuits ICs. Also, the fabrication cost of liquid crystal display device is further increased due to the relatively large size of PCBs and FPC.
Liquid crystal display devices have the disadvantage of low picture quality since the common voltage Vcom is changed. This problem of low picture quality is caused by the load generated with the crossing of the common electrode 71, 81 supplied with the common voltage Vcom and the data lines D1 to Dm supplied with the data voltages.
FIG. 6 is the example of illustrating the crossing of the data lines and the common electrode 71 in the Storage-On-Common method. FIG. 7 is the example of illustrating the crossing of the data lines and the common electrode 81 in an In-Plane Switching mode (hereinafter, referred to as “IPS”) where the pixel electrode PIX and the common electrode COM are formed on the same substrate. As shown in FIGS. 6 and 7, if the data lines D1 to Dm are orthogonal to the common electrode 71, 81, an electric coupling occurs between the crossing of the data lines D1 to Dm and the common electrode 71, 81. Due to the electric coupling between the data lines D1 to Dm and the common electrode 71, 81, the common voltage Vcom becomes inconstant by the data lines supplied with the data voltage by the unit of one horizontal period.